Works great on Citrix VM as well.LinkRamesh NatarajanJuly 25, 2009, 12:31 [email protected], @Marcus, @Vidooshak,Thanks for your comments.
Owing to the 10-bit data bus on the parallel side, most SerDes cores on the market require a reference clock to the PLL with a frequency that is one tenth of the serial data rate.
As a result, when multiple SerDes cores are integrated into a single chip, there will be the same number of frequency multipliers as the cores on the chip.
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To reduce cost, this high-speed clock is normally generated from an off-chip low-frequency quartz crystal.
PCI Express allows timing jitter (caused by ISI, power supply noise, etc.) up to 60% of the bit time on the input data stream.
As shown in Figure 11, a DLL is similar to a PLL with the VCO replaced by a VCDL (Voltage Controlled Delay Line).
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In addition, the output impedance of the line driver has to be able to switch from low impedance to high impedance and vice versa during these low power states.
Most SerDes cores offer BIST functions in the form of a PRBS (Pseudo Random Bit Sequence) pattern generator in the Serializer and a corresponding pattern checker in the De-serializer.
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ARM Architecture Reference Manual - ARM Information Center
Similar to SATA and SAS, PCI Express has several power management states that require the line driver to maintain a constant common-mode level with zero differential outputs during Electrical Idle.
Consequently, there is a need to minimize power and size regardless what process technology is used.
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